The invention relates to an integrated circuit including an input buffer circuit for generating an inverted and a non-inverted logic output signal in dependence on an input signal switching between a first and a second voltage, having a first and a second input gate, each having an input for receiving the input signal and an input for receiving a signal derived from a chip select signal, and each having an output for providing a first and a second intermediate signal, further including a first and a second amplifier circuit for converting the intermediate signals into the logic output signals.
Such an integrated circuit is disclosed in the U.S. Pat. No. 4,807,198, which describes an integrated circuit in which the input signal and the chip select signal are applied to two input NOR gates, whose outputs are each connected via a hysteresis circuit to cross-wise coupled NAND gates, which form a latch. The two data paths thus formed have different switching points which cause, when the input signal increases or decreases, the output signal present to be deselected before the new output signal is selected. The different switching points of the data paths are realized by a suitable dimensioning of the relevant transistors of the input gates and hysteresis circuits. The process spread which is unavoidably caused during production results in unwanted inaccuracies.